The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of reducing the area occupied by an auto precharge circuit.
In a typical semiconductor memory device, the word line is automatically disabled upon completion of a write operation in response to a write command that includes an auto precharge command. The disabling is performed by an auto precharge control circuit included within the semiconductor memory device. When the write command, which includes the auto precharge command, is inputted to the semiconductor memory device, the auto precharge control circuit automatically generates the precharge signal at a predetermined time point after the input operation of the semiconductor memory device is finished. In response to the precharge signal, a row activating unit (or row decoder) disables the word lines belonging to the cells that have finished the write operation.
An auto precharge block is present for each memory bank, and memory bank information is carried in an internal column access strobe command signal (ICAS) that is inputted to the auto precharge block. A time point at which the auto precharge signal is generated depends on whether a signal is a read signal or a write signal. That is, when the signal is a read signal the auto precharge signal is generated just after the read command, whereas when the signal is a write signal the auto precharge signal is generated at variable time points after the write command, since the write recovery time (or tDPL: data in to precharge command; hereinafter, referred to as ‘tWR’) is required.
The tWR is a period of time ranging from when the data is stored in a unit cell of the memory device until the precharge operation is performed. That is, the tWR is a minimum time period in which data can be sufficiently stored in the active bank without interrupting the precharge command.
In order to secure the tWR, a delay unit is included in the auto precharge block. FIG. 1 shows an embodiment in which a delay unit is included in an auto precharge circuit.
Referring to FIG. 1, the auto precharge circuit 10 includes: a read auto precharge signal generating unit 20, which receives a predetermined predeterminedsignal to generate a read auto precharge signal; a write auto precharge signal generating unit 30, which delays the read auto precharge signal for a predetermined predeterminedtime to generate a write auto precharge signal; and an auto precharge signal output unit 40, which receives the read/write auto precharge signals and outputs an auto precharge signal. The write auto precharge signal generating unit 30 includes a first delay unit 31 shifting the read auto precharge signal such that it is synchronized with the internal clock signal, and a second delay unit 32 that delays the read auto precharge signal for a predetermined predetermined time in accordance with the CAS latency CL.
The read auto precharge signal generating unit 20 receives ICAS<0:3> and IA<10> as inputs. ICAS<0:3> and IA<10> are obtained by converting a CAS command, which consists of an external write or read command, and an address signal address<10>, which determines whether or not the signal is the auto precharge, into internal signals. The internal CAS command ICAS<0:3> includes the bank information contained in the internal signal, and the generated time point varies in accordance with whether the signal is a read or a write signal (shifted 2 clock cycles from the external write signal). Also, the internal address signal IA<10> has its generating time point varied in accordance with whether the signal is a read or a write signal (shifted 2 clock cycles from the external write signal). The above example assumes that the semiconductor device has 4 banks.
Since each memory bank includes an auto precharge circuit 10, when there are 4 banks, four read auto precharge generating units 20, four write auto precharge signal generating units 30, and four auto precharge signal output units 40 are necessary. In a semiconductor device, the circuit area increases as the number of banks increases, and thus cell efficiency decreases.
The block shown in FIG. 1 operates as follows.
In the read auto precharge case, ICAS<0> and IA<10> are generated in response to externally input commands, and ICAS<0> and IA<10> are inputted to the auto precharge signal generating circuit of the designated bank. The read auto precharge signal generating unit 20 holds an auto precharge detect signal APCG_DETB at a low level by a latch operation. The read auto precharge signal Read_APCG<0> of a low level is generated if a burst end signal is received during a burst operation.
It is not necessary to secure the tWR in the read operation, and thus the read auto precharge signal Read_APCG<0> is not inputted to the write auto precharge signal generating unit 30, and is instead directly input to the auto precharge signal output unit 40 where the auto precharge signal APCG<0> is output.
In the write auto precharge case, similar to the read auto precharge, the ICAS<0> and the IA<0> are generated in response to the externally input commands and the signals are then input to the auto precharge signal generating unit 20 of the designated bank. The auto precharge detect signal APCG_DETB maintains the low level by a latch operation, and the read auto precharge signal Read_APCG<0> is generated if the burst end signal is received. However, in the write auto precharge case, the read auto precharge signal Read_APCG<0> must pass through the write auto precharge signal generating unit 30 in order to secure the tWR in the write operation. The write auto precharge signal Write_APCG<0>, which is delayed for tWR through the first and second delay units 31, 32 of the write auto precharge signal generating unit 30 is output from the auto precharge signal generating unit 40 as the auto precharge signal APCG<0>.
The write signal WT is supplied so that only one of the write auto precharge signal and the read auto precharge signal is selected and output.
The write auto precharge signal generating unit 30 shown in FIG. 1 must be formed in each bank even though each write auto precharge signal generating unit 30 has the same structure, resulting in the area of the semiconductor device being unnecessarily large.